As the speed of data processing devices has increased, a common bottleneck to electronic systems performance is the rate at which data can be transferred (bandwidth) between memory device and a data processing devices. For example, a microprocessor will read data from and write data to a memory device. In the event the memory device cannot provide data at a fast enough rate, the microprocessor will not able to operate at its maximum speed as it may undergo "wait" cycles as it waits for data. Such wait cycles can be of particular concern in high speed systems, such as synchronous systems.
The data bandwidth between two semiconductor devices (chip-to-chip bandwidth) can be increased by increasing the data word width (the number of data bits in parallel that are transferred between the two devices) and/or increasing the data output frequency (the speed at which the data bits are transmitted). Increasing the data word width has the effect of increasing the amount of current drawn by a device, as the number of outputs that must be switched between high and low logic levels increases. Increasing the data output frequency also results in increased current consumption, as the outputs are switched more often. Drawing increased current is undesirable, as the power supply to a semiconductor device may not be capable of handling such an increased current load.
Increased current draw also translates into increased power consumption. Low power consumption in a semiconductor device is an important feature, particularly for portable (battery powered) electronic systems.
Both methods of increasing chip-to-chip bandwidth (wider word widths and increased data output frequency) have the effect of increasing noise on the power supply lines. Such increased noise can affect chip functionality. In particular, input buffers which receive input data and various control signals can be susceptible to such noise, which can adversely affect data values and device control.
The power consumption caused by chip-to-chip communication is further exacerbated by the capacitance of the communication bus that connects the chips together. The relative distance between two chips is typically much greater than the distance between two communicating circuits in a semiconductor device. In addition, the bus lines that make up a communication bus are typically much thicker than the metal lines within a semiconductor device. These factors result in chip-to-chip communication buses having a relatively high capacitance. As a result, the output circuits of a semiconductor device must be capable of sinking and sourcing large amounts of current in order to drive the bus lines between logic values. This requirement results in most output circuits consuming more power than the other circuits within a semiconductor device.
One approach to reducing the noise involved in the switching of output circuits involves comparing the bits first received data value with a subsequently received second data value. If half or less than half, of the first value data bits need to be switched in order to generate the second data value, the second data value is allowed to be driven on the communication bus. However, if more than half of the first value data bits must be switched to generate the second data value, the second data value is first inverted, and then allowed to be driven on the communication bus. This arrangement has the effect of minimizing the amount of switching on the data bus, so that at most, one-half the data bits will need to be switched. This is in contrast to conventional output circuits which may need to switch all the data bits when changing from a first data value to a second data value. It is noted however, that such compare arrangements require an extra communication bus line in order to indicate if the data bus is being driven with an actual data value (i.e., half or less of the data bits needed to be switched) or an inverted value (i.e., more than half of the data bits needed to be switched). The process of reducing the number of transitions necessary to generate subsequent data values is often referred to as "low weight" coding.
"Bus-Invert Coding for Low-Power I/O" appearing in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pages 48-59 and dated March, 1995, by Stan et al., and incorporated by reference herein, proposes a data compare arrangement as described above. As best illustrated in FIG. 8, Stan et. al. samples an external bus, compares the sampled data with data that is to be written on the bus, and inverts or does not invert the data accordingly. One problem with this approach is that the time required to sample the external bus can take too long, making the output circuits inappropriate for high speed systems. In addition, in the arrangement of Stan et al., the external bus could be in a "grey" zone (undeterminable logic) voltage level, which could cause the sampling input buffers to consume excess power and perhaps oscillate ("thrash"), which could cause the majority voter to malfunction.
"A 50% Noise Reduction Interface Using Low-Weight Coding", appearing in 1996 Symposium on VLSI Circuits Digest of Technical Papers, pages 144-145, by Nakamura et al., incorporated by reference herein, discloses another such coding arrangement Nakamura et al., however, can suffer from the same drawbacks of Stan et al. Furthermore, Nakamura et al. teaches the transmission of a low weight code from a transmitting circuit to a receiving circuit, and provides no teachings on taking into consideration a previous inversion value when determining whether or not to invert the next data value. As a result, the approach of Nakamura et al. may cause more than half of the data bits to be switched on the external bus, in the case where exactly half the bits don't match, and the previous data word had been inverted. This case will be explained in more detail in the description of the preferred embodiment that follows below.
"A 500-MHz 4-Mb CMOS Pipeline-Burst Cache SRAM with Point-to-Point Noise Reduction Coding I/O", appearing in IEEE Journal of Solid-State Circuits, dated November 1997, by Nakamura et. al., incorporated by reference herein, discloses another coding scheme. It is noted that Nakamura et. al. does not disclose any power saving mechanisms for the output buffer or the majority voter circuit. In addition, Nakamura et al. may not provide the speed performance necessary for very high speed memory devices.
Accordingly, it would be desirable to provide an output circuit that decreases the number of times output driver is required to switch the logic level on a chip-to-chip communication bus. It would also be desirable to provide such an output circuit with large chip-to-chip data bandwidth capability, low power consumption and low power supply noise characteristics.